The following scenario should give errors as assertions should be violated (on purpose). But, the check is extending from one “run” to the next, and the assertion is being checked as valid. I’ve used $rose(valid) so that the assertion begins only when valid has asserted HIGH, not for every clock cy…

In reply to Husni Mahdi : By saying you don’t want the assertion checking “from one “run” to the next”, I think you want this to fail if valid falls and ready has not been asserted. I think you might look to see if this meets your needs: $rose(valid) |-> ready[=1] within valid[*6:10];

Timing Assertions

SystemVerilog

Husni_Mahdi February 23, 2023, 5:05pm 8

In reply to Shubhabrata:

What is the purpose of the clocking block here.