Timeslot

SystemVerilog
1

What is a timeslot related to SystemVerilog Scheduling semantics? Is it defined as a timescale?

2

Hardware description languages like Verilog, SystemVerilog, and VHDL are defined with discrete event-driven simulation semantics. That means simulation time is defined as an integer, and all signal changes (events) scheduled for the current or a later time are put into queues. A queue for a discrete time in the future is created as soon as an event needs to be scheduled for that time. As soon as all the events for the current time are finished, the simulator looks for the next time queue where an event is scheduled, advances the current time to that next time, and the process repeats until there is nothing left to do, or it executes a $finish. Time is discrete because the simulator only executes the times where events are scheduled, and skips over everything else. You can think of each queue for a single time as a timeslot.

A `timescale 1ns/1ps directive means that all the delays that follow (like #5) are interpreted to be in nanoseconds and any fractions will be rounded to the nearest picosecond. Remember that all delays are represented as integers. The simulator knows nothing about seconds or nanoseconds, only unit-less integers.

In order to synchronize the scheduling of events across different modules with different timescales and precisions, the simulator picks the smallest time precision across the entire design and assigns that the value of 1 time unit. If the smallest precision was 10ps, that becomes the global value of 1 time unit. So if there were a module with a timescale of 1ns/1ns and there was a delay of #12.3, that would be rounded to 12ns and then scaled to an integer of 1200. (1200x10ps= 12ns)

3

Hi Dave,

I am not able to understand the usage of timescale.
if simulator understand only integer then #integer would have been enough for simulator to understand when a perticular event has to be executed.
can you please elaborate on this point.

Thanks and Regards,
Raj

4

In reply to dave_59:

Hi,

Can I consider a timeslot as a time unit(smallest time precision)? In realtime, time taken to clear all queues might vary from one-timeslot to next/another timeslot, but during simulation, the timeslot is represented as the time unit, is this correct?

Thanks

5

In reply to DDN: SystemVerilog defines a time slot as the region of all activity that happens while simulation time remains a constant. The elapsed CPU time is irrelevant.

The smallest possible increment when advancing from one time slot to the next is represented by the global time precision. When discussing input sampling in clocking blocks, this is conceptually represented by the special #1step delay keyword.