Time0 signal checker

SystemVerilog
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6

In reply to mlsxdx:
Sorry to mislead you, but I just realized your module dut has input ports clk and resetn which are wires starting out as unknown values. You have the wire resetn connected to the bit rstn. That creates a negedge resetn at time 0 regardless of what happens to clk.

Your testbench can make procedural assignment directly to en to make the checker not fail.

initial begin
      //active region blocking assignment
      dutI.en = 0;
      #10 $finish;
   end

If en happens to be a wire and not a variable, you can use a force statement followed by a release.