Time checking sequence

SystemVerilog
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4

In reply to emin:
function call and task calls with functions and tasks require the empty argument list, in other words the ().


module m; 
  bit f1, a; 
  function f; 
    return 1;
  endfunction
  
  initial begin 
    a=f; // <<< need f()
    $display ("a=%b", a); 
  end 
endmodule
 "Invalid function call: f." "testbench.sv" 8  8

In reply to ben@SystemVerilog.us:

  1. Is it better to use $realtime rather than $time?
    YES>
  2. Are there any differences between always forever and initial forever?
    I don’t believe so; they both work.>
  3. What is the advantage of using data type bit over logic?

With bit, there is no need to initialize the clk. Logic is of course 4 states, but I don’t believe that there is much impact in terms of speed for simulation, maybe less memory.