Time checking sequence

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

Thank you Ben!
Sorry I forgot to initialize the clock. But real problem is, trying to call the function without parenthesis,

()

After adding parenthesis it worked like a charm. I have few more questions regarding your modifications,

  1. Is it better to use $realtime rather than $time?
  2. Are there any differences between always forever and initial forever?
  3. What is the advantage of using data type bit over logic?

Thank you in advance.