Time checking sequence

SystemVerilog
, ,
2

In reply to emin:

A simple error, the TB never clocked because
logic clk; // is initialized to x
COde works OK; made simple mods


module tb;
    bit clk;
     
    realtime delay = 50ms;
     
    function automatic bit check_time();
      // $display("running check time %t", $realtime);
      return ($realtime > delay) ? 1'b1 : 1'b0;
    endfunction
     
    localparam CLK_PERIOD = 1ms;
    // always #(CLK_PERIOD/2) clk=!clk;
    initial forever #10 clk=!clk;  
     
    initial begin
        #100ms $finish;
    end
     
    sequence check_time_s;
        bit res;
        (1, res = check_time()) ##0 (res == 1'b1);
    endsequence
     
    property check_time_p;
        @(posedge clk) check_time_s |-> 1;
    endproperty
    check_delay: assert property(check_time_p) // $display("@t %t PASS", $realtime);
        else $error("Assertion label failed!");
     
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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