Time by time division

SystemVerilog
,
1

Hi all,
I wrote this code to illustrate my problem.


`timescale 1 ns / 1 ns
...
time var1_time;
bit[31:0] var2_hex;

initial
begin
  var1_time = 1986160000ps/1000000000ps;
  var2_hex  = var1_time;
  $display("var1_time = %t", var1_time);
  $display("var2_hex = %h", var2_hex);
  $display("division = %h", 32'd1986160000/32'd1000000000);
end

In the simulation log I got:

var1_time = 2000

var2_hex = 00000002

division = 00000001

I don’t understand the results of the first and second displays.
I was expecting var2_hex = 00000001 (same as the value of the third display)

Maybe there is something hidden in that time/time division :) …
Can anyone please explain ?
Thanks

2

In reply to imed_mabrouk:

The difference that time literals are real numbers scaled to the current timescale. The division result is real, then rounded to an integer as it is assigned to
var1_time. Integer division truncates.

time is just a 64-bit type. This is leftover from early versions of Verilog when the precision of time was defined by the simulator implementation. Now it is just an alias for bit [63:0].