In reply to chr_sue:
So is your claim about “improving simulation speed” an it ought to do that? Or did you measure the speed of their previous undisciplined SV approach against the new SV approach?
Maybe someone did a study of simulation speed of SystemVerilog against VHDL?
TLM can be functional equivalent, cycle equivalent, or even timing equivalent. I would suspect that once you get to cycle equivalent (which I think you would need to verify a design), that TLM has the same number of events on the interface as an undisciplined a “copy and paste” approach. Going further, TLM requires additional overhead to hand off the transaction information vs. the “copy and paste” approach. That said, I doubt the TLM additional overhead is much though - and there is no doubt that the other benefits of TLM out weigh this.
OTOH, I do agree with your first two claims - as I noted similar items in my response to the “Whys of Drivers” post.
WRT your 4th claim, SV only makes sense for the Verilog community. You see this more clearly in the FPGA community where for verification, VHDL is used more often than SV - and UVM is on a decreasing trend where as VHDL’s OSVVM is on an increasing trend.