In reply to Jim Lewis:
This is a misunderstanding. I do not measure Systemverilog vs. Verilog. What I mean is the UVM is heavily employing a specific software technique - transaction-leve-modelling (TLM) - which is reducing the amount of events tremendously. This results in less activity during the simulation and thus increases the simulation speed. Only the so-called transactors (drivers, monitors) are working on the pin-level with all the events. Depending on the amount of code for transactors and TLM-code the simulation speeds-up.
But there are no numbers because we had to compare a traditional TB with a UVM envroment with the same behavior. Nobody did implement and check this.