The syntax of env::type_id::create("abc", this) confuses me

UVM
1

According to my basic knowledge about systemverilog, we can use the operator :: to access a static member of a class.

For example,


class A;
    static function void test();
    endfunction
endclass
class B;
    static A a;
endclass

We can do

B::a::test()

But how can we do the following:

env::type_id::create("abc", this)

When type_id is just a typedef, not a static member of the env class.


`define uvm_component_utils(T) \
   `m_uvm_component_registry_internal(T,T) \
   `m_uvm_get_type_name_func(T) \

`define m_uvm_component_registry_internal(T,S) \
   typedef uvm_component_registry #(T,`"S`") type_id; \
   static function type_id get_type(); \
     return type_id::get(); \
   endfunction \
   virtual function uvm_object_wrapper get_object_type(); \
     return type_id::get(); \
   endfunction

Why is this allowed? I don’t understand the concepts inside.

2

In reply to yorkt:

Here’s a hint : In SV LRM refer section => 8.23 Class scope resolution operator ::

3

In reply to ABD_91:

In SystemVerilog, the class scope resolution operator applies to all static elements of a class: static class
properties, static methods, typedefs, enumerations, parameters, local parameters, constraints, structures,
unions, and nested class declarations. Class scope resolved expressions can be read (in expressions), written
(in assignments or subroutines calls), or triggered off (in event expressions). A class scope can also be used
as the prefix of a type or a method call.

So typedefs are also considered as static member of a class. Thanks.