The difference between various assignment methods

SystemVerilog
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1

Hi:
I would like to ask two questions about the following code.
First, why does the line of code “way1” generate an error? (Variable input ports cannot be driven)
Second, what is the difference between “way2” and “way3”?


module my_module (
  input logic in1,
  input logic in2,
  input logic clk,
  output logic out
);

  always @(posedge clk) begin
    out <= in1 & in2;
  end
endmodule

interface inta(input clk);
  logic test;  
endinterface

module top_module;
  logic clk_s = 0;
  
  my_module u_my_module();
  inta u_inta(clk_s);
  //assign u_my_module.in1 =  u_inta.test;      //way1
  initial begin
	force u_my_module.in1 =  u_inta.test;   //way2
	force my_module.in1   =  u_inta.test;   //way3
  end

endmodule

Thank you in advance.

2

In reply to jianfeng.he:

The port declaration
input logic in1; is implicitly
input wire logic in1;. It is a net port, not a variable port. Although “way1” is not a good coding practice, it is not an error to continuously drive an input port that is a net. Your tool is mistaken. See section 23.2.2.3 Rules for determining port kind, data type, and direction in the IEEE 1800-2017 SystemVerilog LRM

The hierarchical reference
my_module.in1 used in “way3” is not valid.
my_module needs to be either a local instance name, or an upwards reference in the hierarchy to a module name. It is neither in your example. If there was a second instance of my_module that reference would be ambiguous. Your tool is mistaken for not making this an error.