// Code your testbench here
// or browse Examples
class reg_a_class;
rand bit [11:0] value;
endclass
class reg_b_class;
rand bit [2:0] value;
endclass
class reg_c_class;
rand bit [1:0] value;
endclass
class reg_d_class;
rand bit [2:0] value;
endclass
class reg_model;
rand reg_a_class reg_a;
rand reg_b_class reg_b[0:7];
rand reg_c_class reg_c;
rand reg_d_class reg_d;
function new();
reg_a = new();
foreach(reg_b[i])
reg_b[i] = new();
reg_c = new();
reg_d = new();
endfunction
function int max_reg_c(bit [0:7] reg_b_mode, int reg_a_over_32);
int result = 0;
int last_bit = 0;
for (int i = 0; i < reg_a_over_32; i++) begin
if (reg_b_mode[i%8] && last_bit == 0)
result++;
last_bit = reg_b_mode[i%8];
end
return result;
endfunction
function void display_reg();
$display("reg_a.value=%0h", reg_a.value);
foreach(reg_b[i])
$display("reg_b[%0d].value=%0h", i, reg_b[i].value);
$display("reg_c.value=%0h", reg_c.value);
endfunction
constraint c1
{
if (reg_d.value == 3'b011)
{
reg_a.value[4:0] == 0;
reg_a.value > 12'd64;
reg_b.or with (item.value == 3'b010 && ((int'(item.index)) < ((reg_a.value[11:5])-1)));
reg_c.value+1 <= max_reg_c(
{
reg_b[0].value == 3'b010,
reg_b[1].value == 3'b010,
reg_b[2].value == 3'b010,
reg_b[3].value == 3'b010,
reg_b[4].value == 3'b010,
reg_b[5].value == 3'b010,
reg_b[6].value == 3'b010,
reg_b[7].value == 3'b010
}
, reg_a.value[11:5]-1
);
}
}
endclass
class top_test;
rand reg_model m_reg_model;
function new();
m_reg_model = new();
endfunction
constraint c1
{
m_reg_model.reg_d.value == 3'b011;
}
endclass
module top;
reg_model model_1;
top_test the_test;
initial begin
model_1 = new();
the_test = new();
for (int i = 0; i < 1000; i++) begin
//assert(model_1.randomize()); // the constraint solver can solve this
assert(model_1.randomize() with {reg_d.value == 3'b011;}); // the constraint solver sometines cannot solve this
//assert(the_test.randomize()); // the constraint solver sometines cannot solve this
//model_1.display_reg();
//the_test.m_reg_model.display_reg();
end
end
endmodule
func_in_constraint - EDA Playground
So this is a weird problem when I am trying to randomize register model in my uvm_test.
Basically the problem is if I randomize the register model directly, the solver can solve.
But if I add my new register constraint in my test and then randomize the test instead(doing this.randomize() in my run_phase), the constraint solver can sometimes solve but sometimes can’t.
If I inline randomize it with {reg_d.value == 3’b011;}, it also can’t solve.
A special constraint is that it calls a function in register model to help me find the max value of reg_d.
The most interesting thing is that I tried riviera, xrun, questa, vcs. It happens in VCS only.
I wonder if my code is wrong in sv LRM or it is simulator’s problem.