Text Substitution Query

SystemVerilog
,
1

I was trying text substitution feature in SV


module Text_Substitution ;

`define HI Hello 
`define H(x) "Hello , x"
`define LO  "`HI, world" 

initial begin
 $display("`HI, world");
 $display(`LO);
 $display(`H(world));
end

endmodule

I get Output ::

HI, world HI, world
Hello , x

Since LRM doesn’t allow text substitution within String literals we observe `HI in first 2 lines of output

So I changed the code to ::


module Text_Substitution2 ;

`define HI Hello 
`define H(x) "Hello , x"
`define LO  { `"HI`", " world" }    //  [X]

initial begin
 $display( { `"HI`" , " world" } );  // [Y]
 $display(`LO);
 $display(`H(world));
end

endmodule

I get different Output across simulators . What should the actual O/P be ?

My understanding is via string concatenation ( via and [Y] ) I should be able to achieve text substitution

I expect the Output to be ::

Hello, world
Hello, world
Hello , world

via each of 3 defines at Top .

2

In reply to MICRO_91:

The code on line [Y] is not legal because the use of `" or `` is not legal outside a text replacement macro.

The code on the next line has two problems. The result of a concatenation of all string literals is an integral typed value. This is to maintain backward compatibility with Verilog. Only if that literal is used in the context of another string type does it keep the string literal context. You would need to write it as
$display(“%s”,`LO);.
The other problem is you want the LO macro to written as
`define LO { `“`HI`”, " world" } for `HI to get replaced with Hello.

And the
`define H(x) “Hello , x” macro needs to be defined as
`define H(x) `“Hello , x`” so that the x gets interpreted as an argument to get substituted.

Make these changes and you get the same results on all simulation