In reply to ben@SystemVerilog.us:
A follow up with assertions. The issue:
With the #100 “a” does not appear to be updated in the NBA Region.
It appears (or behaves) as update in the Active Region.
Assertion samples the “a” in the Preponed, thus flags the error as expected.
Attached files show the simulation results.
http://systemverilog.us/test_blk_ok.sv
http://systemverilog.us/test_blk_err.sv
I get the same results in 3 different simulators.
@ (cb1) a <= 2;
#100 a <=1; // occurs at 250ns
//------
@ cb1; // occurs at 250ns
b <= a;
----------
ap_ab: assert property(@ cb1 a==2 |=> b==2);
** Error: Assertion error.
# Time: 350 ns Started: 250 ns Scope: top.ap_ab File: test_blk_err.sv Line: 19 Expr: b==2