Testbench signal driving right at clock edge, how does the simulator behave?

SystemVerilog
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In reply to silverace99work:

In reply to ben@SystemVerilog.us:
Thanks for the detailed reply Ben! I also find it strange that the non-blocking assignment is evaluated as a blocking one.
Does anybody know why the following line would behave as blocking?

#250ns arbif.cb.request <= 1;

It is puzzlng. The following works though

 initial begin 
  repeat (2) begin
    @ (cb1) a <= 3;
    @ (cb1) a <= 2;
    //@ (cb1) a <= 1;   // NONBLOCKING assignment 
    #100 -> e; 
    @e a <=1; // WITH TH @e
    #200;
  end 
end
t=                 153, a=          2, b=           3
t=                 250, a=          2, b=           3 // <**** a==2 here 
t=                 251, a=          2, b=           2 
t=                 253, a=          2, b=           2
//------------  BUT without the @e
    @ (cb1) a <= 2;
    //@ (cb1) a <= 1;   // NONBLOCKING assignment 
    #100 -> e; 
    a <=1;   // NO @e !!!!!
    #200;
...
t=                 153, a=          2, b=           3
t=                 250, a=          1, b=           3  // <**** a==1 here ????
t=                 251, a=          1, b=           1
t=                 253, a=          1, b=           1

The answer is somewhat related to 1800:4.7 Nondeterminism, but I don’t see the explanation.
Particularly, 4.7 Nondeterminism states One source of nondeterminism is the fact that active events can be taken off the Active or Reactive event region and processed in any order. Another source of nondeterminism is that statements without time control constructs in procedural blocks do not have to be executed as one event. Time control statements are
the # expression and @ expression constructs (see 9.4)
That last line states that with time control (the @ and the #) it is deterministic.
It appears that though they are “deterministic”, they are treated as separate time control; meaning that the (Delay statements) are executed first, and the **(@ event statements)**is executed next. At least that is how simulators seem to work. I don’t believe 1800 addresses that specifically. Maybe the key lies in the fact that the # and the @ are different things, and the # tends to be blocking, whereas the @ is nonblocking.
I’ll seek an answer from people in the 1800 language committee (I am in the assertions committee).
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us