In reply to selmenna:
There are a few question I’d like to ask:
(1) How do you synthesize clas-based objects into hardware?
(2) Emulation is using a very specific Approach synthesizing certain objects, but not all. The problem is how to synchronize these parts. The emulator is providing its own mechanism.
If your simulation runs so long this is definitely not caused by your UVM testbench. It is the RTL which is running so slow. This cannot be accelerated by passing certain TB elements into hardware.
To solve the speed problem you should think about other approaches like increasing you clock frequency on the RTL side.