Testbench clock not toggling

SystemVerilog
,
1

I have a testbench with a clock generator. But, the clock goes to 1 at time 0 and never toggles. I want to know what I might be doing wrong. Code is below -

Testbench -

`timescale 1ns/1ps

module my_tb;

logic clk;

initial
   begin
       clk = 1;
       forever #1ns clk = ~clk;
   end

endmodule

I’ve tried more than one variation of the generator -

always #5 clk=~clk; //this doesn’t work either.

Is my timescale directive messing things up? Is it something else completely ?

2

In reply to Prathyusha Sandilya:

It is something else completely because your code works for me.

Please show a complete example that demonstrates the problem.

Here is what I meant by a complete example

`timescale 1ns/1ps
 
module my_tb;
 
logic clk;
 
initial
   begin
       clk = 1;
       forever #1ns clk = ~clk;
   end
initial begin
  $monitor($time,,clk);
  #10ns $finish;
end
 
endmodule