Hi
I have a question regarding the distribution of verification tasks among different team members. Please correct me if the following is not correct.
If I understand correctly, the testbench architect is required to have a deep understanding of UVM so that he can develop a good, working environment. On the other hand, for the test writer it is more critical to have a deep knowledge of the DUT internals, so that he can bring about different corner cases and go through the verification plan more quickly. I think for the test writer, it is enough to have a general understanding of the concepts, such as how to use constraints, how to override some component by type or instance, etc.
Based on the above, I think the design engineers, if they have some general understanding of UVM concepts, may be best candidates for writing tests. Certainly, though, development of the verification plan and also the golden reference model shouldn’t rely solely on the designers, because then the designers would be checking their own design, which isn’t a good idea. My point is that, if the verification plan and the golden reference model are developed by people other than the designer himself, then the different testcases can perfectly be developed by the designer, as he’s the best person to go through different items of the verification plan.
Please enlighten me if you think the above thoughts are in correct. I would also highly appreciate if I am referred to some material which goes through these kinds of subjects in a systematic manner.
Thanks
Farhad
In reply to Farhad:
Hi Farhad,
the testbench architect is required to have a deep understanding of UVM
IMO, the environment architecting needs also good understanding of the design and its specs, not only UVM. E.g. knowing the different interfaces so that you decide the required Agents in your environment and their types (passive, active, reactive). Then after finishing the agents and their drivers/monitors/sequencers, you may think about the main-sequences to bring-up and configure the DUT with simple directed test (to make sure everything is initially good), then the required scoreboards step and their connections. Later - in parallel with the sequences developments - the reference modeling, checkers, coverage, etc are developed.
I think the design engineers, if they have some general understanding of UVM concepts, may be best candidates for writing tests.
Not agree, as you mentioned later, it is not recommended that the designer verifies its work, instead, verification engineer who understand the specs very well and will create verification plan for it and verify everything, without having a perfect idea about the internal implementation of the design, so no biasing occurs in the verification.
My point is that, if the verification plan and the golden reference model are developed by people other than the designer himself, then the different testcases can perfectly be developed by the designer, as he’s the best person to go through different items of the verification plan.
Not agree with your point, as I mentioned above, IMO the verification engineer who should create the verification plan (before the environment architecting itself) and also who should move on every item in it to develop the required test, sequence, checkers, or coverage collection.
For sure an interaction with the design team will be required especially if there are whitebox modeling and checkers, but the sequences/tests developments and coverage closure are the verification engineer responsibility.