In reply to cgales:
interface ethernet_if(input sig_clk,sig_reset); //clk generation and reset set/unset in top
logic sig_sop;
logic sig_eop;
logic [31:0] sig_data;
logic sig_dval;
logic [3:0] sig_mode;
modport ethernet(input sig_clk, sig_reset, clocking cb);
clcking cb @(posedge sig_clk);
default output #1ns;
output sig_sop,sig_eop,sig_data,sig_dval,sig_mode;
endclocking
endinterface : ethernet_if