file name : package.sv
package count_pkg;
int no_of_transactions = 1;
include "up_down_package.sv"; include “up_down_gen.sv”;
include "up_down_dr.sv"; include “up_down_wrmon.sv”;
include "up_down_rdmon.sv"; include “up_down_refmod.sv”;
include "up_down_sb.sv"; 'include "up_down_env.sv"; include “test.sv”;
endpackage
file name : test.sv
import count_pkg::*;
class my_test
virtual count_if.DRV dr_if;
virtual count_if.WR_MON wr_if;
virtual count_if.RD_MON rd_if;
count_env env_h;
function new(
virtual count_if.DRV dr_if,
virtual count_if.WR_MON wr_if,
virtual count_if.RD_MON rd_if);
this.dr_if = dr_if;
this.wr_if = wr_if;
this.rd_if = rd_if;
env_h = new(dr_if, wr_if, rd_if);
virtual task build();
env_h.build();
endtask
virtual task run();
env_h.run();
endtask
endclass
file name : top.sv
import count_pkg::*;
module
reg clock;
count_if DUV_IF(clock);
my_test test_h;
up_down_counter DUV(.clock(clock)
.din(DUV_IF.din)
.load(DUV_IF.load)
.up_down(DUV_IF.up_down)
.resetn(DUV_IF.resetn)
.count(DUV_IF.count));
initial
begin
clock = 1’b0;
forever
#10 clock = ~clock;
end
initial
begin
if($test$plusargs(“TEST 1”)
begin
test_h = new(DUV_IF, DUV_IF, DUV_IF);
no_of_transactions = 200;
test_h.build();
test_h.run();
$finish;
end
end
endmodule
file name : makefile
Makefile for Memory - Regression Testing - counter
RTL= …/rtl/*.v
work= work library name
SVTB1= …/env_lib/up_down_counter_if.sv …/test/top.sv
INC = +incdir+…/env1 +incdir+…/env +incdir+…/test
SVTB2 = …/test/package.sv
COVOP = -coveropt 3 +cover=bcft
VSIMOPT= -vopt -voptargs=+acc
VSIMCOV= -coverage -sva
VSIMBATCH1= -c -do " log -r /* ;coverage save -onexit mem_cov1;run -all; exit"
VSIMBATCH2= -c -do " log -r /* ;coverage save -onexit mem_cov2;run -all; exit"
VSIMBATCH3= -c -do " log -r /* ;coverage save -onexit mem_cov3;run -all; exit"
VSIMBATCH4= -c -do " log -r /* ;coverage save -onexit mem_cov4;run -all; exit"
help:
@echo ===========================================================================================================
@echo " USAGE – make target "
@echo " clean => clean the earlier log and intermediate files. "
@echo " sv_cmp => Create library and compile the code. "
@echo " TC1 => To compile and run the testcase1 in batch mode. "
@echo " TC2 => To compile and run the testcase2 in batch mode. "
@echo " TC3 => To compile and run the testcase3 in batch mode. "
@echo " regress_12 => clean, compile and run testcases TC1 and TC2 in batch mode. "
@echo " report_12 => To merge coverage reports for testcases TC1, TC2 and convert to html format. "
@echo " regress_123 => clean, compile and run testcases TC1,TC2,TC3 in batch mode. "
@echo " report_123 => To merge coverage reports for testcases TC1,TC2,TC3 and convert to html format. "
@echo " cov_report => To view the coverage report. "
@echo ===========================================================================================================
sv_cmp:
vlib $(work)
vmap work $(work)
vlog -work (work) (RTL) (INC) (SVTB2) (SVTB1) (COVOP)
TC1:sv_cmp
vsim -cvgperinstance (VSIMOPT) (VSIMCOV) $(VSIMBATCH1) -wlf wave_file1.wlf -l test1.log -sv_seed 2975249645 work.top
+TEST1
vcover report -cvg -details -nocompactcrossbins -codeAll -assert -directive -html mem_cov1
TC2:sv_cmp
vsim -cvgperinstance (VSIMOPT) (VSIMCOV) $(VSIMBATCH2) -wlf wave_file2.wlf -l test2.log -sv_seed 1556525292 work.top
+TEST2
vcover report -cvg -details -nocompactcrossbins -codeAll -assert -directive -html mem_cov2
TC3:sv_cmp
vsim -cvgperinstance (VSIMOPT) (VSIMCOV) $(VSIMBATCH3) -wlf wave_file3.wlf -l test3.log -sv_seed 821475296 work.top
+TEST3
vcover report -cvg -details -nocompactcrossbins -codeAll -assert -directive -html mem_cov3
report_12:
vcover merge mem_cov mem_cov1 mem_cov2
vcover report -cvg -details -nocompactcrossbins -codeAll -assert -directive -html mem_cov
regress_12: clean sv_cmp TC1 TC2 report_12
report_123:
vcover merge mem_cov mem_cov1 mem_cov2 mem_cov3
vcover report -cvg -details -nocompactcrossbins -codeAll -assert -directive -html mem_cov
regress_123: clean sv_cmp TC1 TC2 TC3 report_123
cov_report:
firefox covhtmlreport/index.html&
clean:
rm -rf transcript* log vsim.wlf fcover* covhtml* mem_cov* *.wlf modelsim.ini
clear
I am trying to debug the code but I am getting certain errors
error 1 : my_test is of unknown type or did you omit ‘()’ for an instantiation
error 2 : test_h is not a variable
error 3 : Illeagal LHS of assignment
error 4 : new must be used to assign for a class or covergroup handle