In reply to divyadm:
Hi,
To verify the feature for all possible modes, you need to go with the Unit Level verification. Controlling inputs of the unit according to protocol could be a difficult task here. But, exhaustiveness can be reached here as for module/system verification, input set reaching to the Unit could be limited.
Next step is to check, this Unit(having the feature implemented) integration to the module and verifying the integration here.
If the feature you have propagates to different system module regions which are not covered previously, then you need to generate system level use can for this particular feature as well. See where this feature/signals dependent on it propagates. This could be a difficult observation indeed!
Basically you’ll be doing everything. Two main things to note are exhaustiveness of stimuli(Block Level e.g.Formal Verification) and integration checks(on System Level, or Module if function is contained in Module only).