Test does not enter build_phase

UVM
,
1

I have made a simple uvm testbench for a simple processor. The compilation is done successfully. But when I start the simulation, the test does not seem to enter the build phase and the simulation is stuck at time 0.


class core_test extends uvm_test;
    `uvm_component_utils(core_test)
    
    core_env core_env_h;
    virtual interface reg_if reg_vif;
    
    core_agent_config core_agent_config_h;
    memory_agent_config memory_agent_config_h;
    
    function new(string name, uvm_component parent);
        super.new(name, parent);
        `uvm_info("core_test", "Test created", UVM_LOW)
    endfunction
    
    function void build_phase(uvm_phase phase);
        super.build_phase(phase);
        `uvm_info("core_test", "build", UVM_LOW)
        core_env_h = core_env::type_id::create("core_env_h", this);

        if(!uvm_config_db #(core_agent_config)::get(this, "", "core_config", core_agent_config_h))
            `uvm_fatal("CORE_TEST", "Failed to get configuration object");

        if(!uvm_config_db #(memory_agent_config)::get(this, "", "memory_config", memory_agent_config_h))
            `uvm_fatal("CORE_TEST", "Failed to get configuration object");

        reg_vif = core_agent_config_h.reg_vif;
        memory_agent_config_h.test_name = "diag.hex";
        `uvm_info("core_test", "end of build", UVM_LOW)
    endfunction
    
    task run_phase(uvm_phase phase);
        phase.raise_objection(this);
        wait_for_test_done();
        phase.drop_objection(this);
    endtask
      
  endclass: core_test

snippet from the top module:


    initial begin
        $display("creating config objects");

        memory_agent_config_h = new();
        core_agent_config_h   = new(core_vif,reg_vif);

        uvm_config_db #(memory_agent_config)::set(uvm_top,"", "memory_config", memory_agent_config_h);
        uvm_config_db #(core_agent_config)::set(uvm_top ,"", "core_config",core_agent_config_h);
        $display("Starting test");


        run_test("core_test");
    end

transcript:


# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(217) @ 0: reporter [Questa UVM]  questa_uvm::init(+struct)
# creating config objects
# Starting test
# UVM_INFO D:/GraduationProject/GPCore/uvm/core-components/c_core_test.svh(14) @ 0: uvm_test_top [core_test] Test created
# UVM_INFO @ 0: reporter [RNTST] Running test core_test...
2

In reply to OYounis:

Your problem might be caused by

wait_for_test_done();

How does it look like?

3

In reply to chr_sue:
It is a simple task that waits for the program counter to reach a certain value. I guess if it was the problem, the core_test would have no problem entering the build_phase.

4

In reply to OYounis:

Are these messages the only output in the transcript? If the simulation is hung, you may not see all the messages due to the way the output is cached. What is displayed when you break the test.

Remove the wait_for_test_done() and see what happens.

You shouldn’t create any configuration objects outside of the UVM environment. You should use the config_db() to pass your virtual interface handles to uvm_test_top. Create your configuration objects in the test and assign the interface handles to the objects in the build_phase() of the test.

Your config_objects should also extend uvm_object and be registered with the factory.

5

In reply to OYounis:

IMO i remember once in the past happened to one of my colleagues and it was really weird because the entire environment was completely fine. Try to add “;” to your uvm info. That was the issue he got but no idea why it should not work without. Give it a shot. Regards

6

In reply to Rsignori92:

Sorry, but this is not legal. Some simulators are tolerating this others not.
My recommendation is to put in more `uvm_info calls to get more detailed information about the build_phase.
But I believe your problem is in the wait_for_test_done().

7

In reply to chr_sue:

Perfectly agree, is not legal, but you know it could be worthy on top of that it doesn’t really harm. Anyway if even 1ns advanced then you should be seeing some prints. Is it hanging at 0 time ? Well it could be.