Ternary operator in Verilog

SystemVerilog
1

Dear Dave,

I hope you are doing good and you are fine.

Please help me for the following query :

Can we use ternary operator in-order to design a Priority Encoder?

I found if I use nested ternary operator it works like a case statement.

Also I want to understand how it justifies that Ternary operator is right to left associativity?

Thanks
Susmita

2

In reply to sush:

Can we use ternary operator in-order to design a Priority Encoder?
{Ans} Yes. As you have already worked out its working as a case statement. And case give priority to its first switch statement more than second switch and so on - Thus works as a priority encoder.

I found if I use nested ternary operator it works like a case statement.
{Ans} True.

Also I want to understand how it justifies that Ternary operator is right to left associativity?

{Ans} So that it can implement a code exactly same as a case statement-

if(cond1) y=a ;
else if(cond2) y=b ;
else if(cond3) y=c ;
else y=d ;

y = cond1 ? a : cond2 ? b : cond3 ? c :d ;

where cond1 has priority of execution over cond2 and so on…
which is again a priority encoder.

A very nice example is here :

Thanks

3

In reply to @nurag:

Thanks for such a nice reply.

It helped me to understand the concept.

Susmita