In reply to ben@SystemVerilog.us:
Hi Ben
Thanks for your reply. I full understand your answer to it and it was really exaustive one.
Question : While building the scorboard(checker) I end up modelling the design.
Sometime it gets complex and my checkers wont be stable for all the possible scenarios ,
dont know if my approach is right. Any thoughts on it ?
Lets take a counter design which output a count value. The counter update happen on many input conditions. As inputs are many I cannot use assertions(Am ).
Now as I understand I take the same input and end up modelling how the output count should change depending on these numerous inputs.
Do you suggest any other way?
Your suggestions would be helpful.
Avinash