In reply to Avinash:
Good question. Given the set of requirements, I approach the development in a bottom up approach, particularly since there are templates or other automation to build the the higher level structures (more on tools below). I also like the idea of building something fast, and then refining it. Thus,
1) Define the interfaces
This will define the signals that need to be driven
2) define the sequence item (the transaction) and some constraints
That defines what will be driven and with which constraints. I believe that the constraints can be refined later on, but easy known ones could be defined here.
3) define the driver
4) define the agent and environment
5) define top
6) do a sanity check
Hopefully, you also added assertions in the interface and a checker or module bound to the DUT.
7) build the rest of the Testbench units (monitor, checkere, etc)
Also refine the constraints and tests.
On tools, there are vendors who provide templates to help in the design of the UVM; examples of such vendors include Mentor and dvteclipse. I also saw (and know) that there are UVM template generators for building the basic UVM structure. One can also use an existing UVM design and modify the structure for the new needs.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115