Task synthesis in verilog

In reply to dave_59:

OK, then - for synthesis - Tasks had better use blocking assignments only (or assign the signal in the calling block itself) and thus they behave like any other “one line” non-blocking assignement in the always block. Therefore Task are not intended to be very complex, their sole purpose is to save typing for repetitive structures, to make the code less redundant, but their purpose is not to break down the design into independent units. I guess it makes little sense to call an (automatic) Task only once within an always block (within the same cycle) bacause then it will not save any redundant typing. Am I right about that?

Then if I am not mistaken events (to sync processes) are not for synthesis either (exept for the posedge clk).

Do you think the iff keyword could be what I am looking for (to kick off a process by enabling it and then to make it stop when it is finished) ?