In reply to mbence76:
You are correct, a task without any blocking statements is essentially a function. Verilog requires functions to have return values and only be part of an expression. But SystemVerilog added void functions that you would use instead and guarantee that they have no blocking statements.
You are also correct that for RTL synthesis you can only have one blocking event. There have been other behavioral synthesis tools that did accept more than one, but they have not been very successful.