Task synthesis in verilog

In reply to mbence76:

The issue you have discovered is that using non-blocking assignments to the output argument of a task/function gives you unexpected results. Input arguments get copied upon entry, and output arguments get copied upon exit of the routine. When using a non-blocking assignment to the output argument, the “old” value gets copied out. The next time you call your task, the output argument has the “new” value from the non-blocking assignment.

So you can change your task to assign yt_out directly

task count (input [3:0] in);      
begin
    yt_out <= in + 1;
end
endtask

Or use an intermediate variable

task count (input [3:0] in, output [3:0] out );      
begin
    out = in + 1;
end
end task
reg [3:0] temp;
always @(posedge clk)
begin
   
   yt_cc <= yt_cc + 1;  // cc = cycle counter
   count(yt_in, temp);
    yt_out <= temp;
end

See this discussion for more info.