The task or function gets in-lined, meaning the code inside the routine gets inserted at the place where it was called.
Hello Dave,
I am a newbie here both on this forum and with Verilog as well. You are a professional in this field, I have no doubts, but this statement about Tasks does not seem to be right. Please help. I am trying to grasp Tasks, I have been reading about them for days now and I still do not get it. They do not work as expected by what I have read so far. Here is my code that I ran in my simulator:
module alma();
reg clk = 0;
always #1 clk <= !clk;
reg [3:0] yt_in = 1; // yt = yes task
reg [3:0] yt_out;
reg [3:0] yt_cc = 0;
reg [3:0] nt_in = 1; // nt = no task
reg [3:0] nt_out;
reg [3:0] nt_cc = 0;
task count (input [3:0] in, output [3:0] out );
begin
out <= in + 1;
end
endtask
always @(posedge clk)
begin
yt_cc <= yt_cc + 1; // cc = cycle counter
count(yt_in, yt_out);
end
always @(posedge clk)
begin
nt_cc <= nt_cc + 1; // cc = cycle counter
nt_out <= nt_in + 1;
end
endmodule
My yt_out signal gets assigned one clock cycle later than nt_out. Is this ok? Is this how Tasks supposed to work? (My two cycle counters run parallel, their values are equal, no problem.)
(Unfortunately the picture insertion button here works the same way as the link button right next to it, it is a bug, so I cannot insert the simulation waveform screenshot.)
Thank you very much
Miklos