SystemVerilog UVM Register Out-of-Bounds Access

UVM
,
1

I have generated a register model (say I have registers defined from address 0x0 to address 0x100). Now, in my SystemVerilog UVM testbench, I would like to perform a read/write to an address location that is out-of-bounds (e.g. 0x104) to make sure that the DUT recovers properly from accessing an invalid address. How can I do that in my uvm_reg_sequence?

Typically, if I write a valid address, something like this would work:
model.tx_cmd.write(status, value, .parent(this));

How should I change the above command to write an out-of-bounds location?

2

I dont think UVM have anything in-built for this.

As per my understanding this can be achieved in two ways:

  1. Adding dummy register for invalid address range.
  2. Manually make the bus transaction by providing invalid/out-of-bound address.

Regards,
Karandeep