SystemVerilog unsized decimal number

SystemVerilog
,
1

Dear all,

Given a variable or net like :

logic [31:0] p;

When this variable/net is assigned un unsized decimal number, i.e :

assign p = 0; // , 1 , 129, 1234567789, or any unsized decimal number

I am wondering how this unsized value is assigned :

  • In case of value > 32 bits
  • In case of value < 32 bits

I want to know when the value is truncated, any padding with zeros is performed ? The LRM is not clear for me

I hope its is clear !

Thank you

2

Section 10.7 of the LRM discusses assignment extension and truncation. Can you explain what confusion you have after reading this section?

3

Thank you @cgales for your reply !
It is more clear reading this section.

However I am wondering then what is the size of RHS for unsized values like :

  • decimal number values : 0 , 1 , 129, …
  • a based unsized literal constant : 'd10, 'h10, …

Thanks

4

Section 5.7.1 of the LRM discusses Integer Literal Constants and how unsized numbers are handled.