SystemVerilog reason of not putting always in program block

[dave_59]

Why system verilog does not allow always block in program scope?

The program block came from the Vera verification language that was donated to SystemVerilog. In Vera, a program was a single procedure that represented the “test”. Your test was started at time 0 and when the test terminated, the program terminated the simulation. If you needed multiple test threads, you either had to use the fork statement to start it, or use multiple programs. When the last program terminated, the simulation terminated. As part of the integration with SystemVerilog, the prog…