SystemVerilog reason of not putting always in program block

[sanjog_garva]

@dave_59 Hi dave according to LRM we don’t put always block in program block because always are intended to run indefinitely but we can put initial with forever why ?

Reason i think of is always generate synthesisable rtl code that behaves like hardware but initial is not and we want to program to terminate after the test is completed that is one reason i got that we not put indefinitely running loop and i also know it came from vera but why initial forever allowed when we don’t want indefinitely running loop

[dave_59]

Why system verilog does not allow always block in program scope?

The program block came from the Vera verification language that was donated to SystemVerilog. In Vera, a program was a single procedure that represented the “test”. Your test was started at time 0 and when the test terminated, the program terminated the simulation. If you needed multiple test threads, you either had to use the fork statement to start it, or use multiple programs. When the last program terminated, the simulation terminated. As part of the integration with SystemVerilog, the prog…

[Tobias187]

Hi Dave, at the end of your blog, you have mentioned virtual interfaces, can you share the link here. becoz I can’t find it. Thanks in advance

[dave_59]

https://share.google/aimode/LAkBXQdccog3x86kJ

🧠 Abstract-Concrete class pair method in UVM—An Alternative to Virtual...

[Tobias187]

Hi Dave, this concrete class approach amazes me who is just a newbie to the DV area. But at the end of the day we are going to verify a design. so why does one approach concerns another is a question I wanna make clear to myself. can I expect your insight on this?