SystemVerilog-Real Number Modeling (SV-RNM)

SystemVerilog
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1

As far as I’ve understood V-RNM (Verilog Real Number Modeling) is enabled by the “wreal” data type.

How is the RNM enabled in SV ?
Is it with the “real” data type? Or how?

Please provide some guidance :)
Thank you!

2

In reply to stefaniecg:

wreal is a tool specific feature that what used before RNM was added to the SystemVerilog 1800-2012 standard.

There are two features in SystemVerilog that address RNM issues: user-defined nettype and the interconnect net/port. These get used with packages of real data types which usually come pre-defined with your tool. Hopefully one day they will become part of the standard.