SystemVerilog Implicit Constraint

SystemVerilog
,
1

Hi all,

Just another question on Implicit Constraints

Here’s the current situation on the Constraint and the following classes that I have currently written.

class the_address;
  rand bit [31:0] addr;  

endclass :  the_address
  
typedef enum {BRANCH, LOAD, STORE, IMM} opcode; 

class decode extends the_address; 
  rand opcode opcode_num; 

  constraint find_opcode 
  { 
    // using the enum opcode as the condition - shows correct
    if (opcode_num == BRANCH)        addr[6:0] == {7'b1100011};
    else if (opcode_num == LOAD)     addr[6:0] == {7'b0000011};
    else if (opcode_num == STORE)    addr[6:0] == {7'b0100011};
    else if (opcode_num == IMM)      addr[6:0] == {7'b0010011};
  }
endclass  : decode

initial begin
    decode bit32;
    bit32 = new; 

    repeat(10) begin
        if(bit32.randomize() == 1)
        begin
            $display("%b    Opcode: %s\n", bit32.addr[6:0], bit32.opcode_num);
        end
    
    else
      $display("RANDOMIZATION FAILED \n");
    
    end

    $finish;
end

It does show the correct result that I desire as shown below:

1100011 Opcode: BRANCH

0100011 Opcode: STORE

0100011 Opcode: STORE

0000011 Opcode: LOAD

0000011 Opcode: LOAD

1100011 Opcode: BRANCH

However, when I make some changes on the constraint - such as:

class decode extends the_address; 
  rand opcode opcode_num; 

  constraint find_opcode 
  { 
    if (addr[6:0] == 7'b1100011) opcode_num == BRANCH;
    if (addr[6:0] == 7'b0000011) opcode_num == LOAD;
    if (addr[6:0] == 7'b0100011) opcode_num == STORE;
    if (addr[6:0] == 7'b0010011) opcode_num == IMM;
  }
endclass  : decode

The result I get is the following:

1111111 Opcode: IMM

0111011 Opcode: IMM

0100010 Opcode: STORE

0001110 Opcode: BRANCH

0100000 Opcode: STORE

1001000 Opcode: LOAD

Is there something that I am doing off? I even tried putting a bidirectional constraint operator on the first constraint that I have used, and it still shows the correct result. The only reason why I tried the second constraint method is to show that if the bidirectional equivalence works, then the constraint should show the same result both ways.

Any help or tips would be appreciated.

Sangwoo.

2

You are confusing bidirectional effects with equivalence.

When you have the constraint

if (addr[6:0] == 7'b1100011) opcode_num == BRANCH;

It just means that complementary constraint

if (opcode_num != BRANCH)  addr[6:0] != 7'b1100011

must also be true.

3

Oh, but in terms of equivalence constraints, if

if (addr[6:0] == 7'b1100011) opcode_num == BRANCH;

is true, then I thought the inverse,

if (opcode_num == BRANCH)  addr[6:0] == 7'b1100011

would also be true… Can you explain on why this is not the case?

4

Because that is not the way implication gets defined.

5

I was just asking that if something can be expressed using equivalence constraints, can I also use implication constraint to express the same thing?

6

In your first constraint, the condition of the if sentence is opcode_num. There are only 4 random results of it:BRANCH,LOAD STORE,IMM.
In your second constraint, the condition of if sentence is addr[6:0]. There are 2^7=128 random results.

means that if addr be other value(except other 3 addr in constraint), opcode_num could also be BRANCH. If you want to do the implication cosntraint ,you should add the constraint sentence as Dave said.

7

That cleared up a lot of things, thanks!