[SystemVerilog] Guideline on when to use logical (`==`) vs. case equality (`===`)

In reply to No:

I cannot think of any use cases where you should prefer the logical equality, i could highlight that basically if you use bits or 2 state arrays/signals in tb there is no sense in using the === .

Usually in Digital modelling is recommended to use === , unless you have some additional checking for unknown values, since the nodel should know and notify when x/z occurs
Regards