Systemverilog cross coverpoint of a specific logical expression

SystemVerilog
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1

Hi, I am new to verification academy and systemverilog/uvm so forgive me if this is trivial. I am currently trying to get the a cross coverpoint to catch the condition that (a==b) && (c==d), regardless of what value they are. I have tried the following crosses and none of them seem to be working.

covergroup abcd_tracking with function sample (bit [7:0] a, bit [7:0] b, bit [7:0] c, bit [7:0] d);
  coverpoint a {   
    bins a_bin[1] = {[0:$]};
  }
  coverpoint b {   
    bins b_bin[1] = {[0:$]};
  }
  coverpoint c {   
    bins c_bin[1] = {[0:$]};
  }
  coverpoint d {   
    bins d_bin[1] = {[0:$]};

   abcd_cross : cross a,b,c,d 
  {
    bins abcd_bin =  abcd_cross with( (a==b) && (c==d) );

  }

   abcd_cross_2 : cross a,b,c,d 
  {
    bins abcd_2_bin =  ( binsof(a) intersect(b)  &&  binsof(c) intersect(d) );

  }

   abcd_cross_3 : cross a,b,c,d 
  {
    bins abcd_3_bin =  ( binsof(a) intersect{[0:$]} with (a==b)  &&  binsof(c) intersect{[0:$]} with (c==d) );

  }

This should actually be an illegal condition that never gets hit, but the 3 cross coverpoints seem to be constantly getting hit even though after checking with my log files, the sampled variables don’t meet the condition I am trying to define in my cross coverpoint. What is the proper syntax for catching this particular condition: " (a==b) && (c==d) " ?

2

In reply to DK_513:

You have a number of syntax errors, but event beyond that, I think you have some misconceptions on how coverpoints and crosses work.

Your four coverpoints have only one bin for all possible values. That means each bin gets hit on the first sample with any value, which is 100% coverage for each of the four coverpoints on the first sample. And since a cross creates bins for all possible bin combinations, you only get one cross bin on the first sample. So each of the three crosses are covered on the first sample.

If you want a separate bin for each value of a coverpoint, you need to write

coverpoint a {   
    bins a_bin[256] = {[0:$]};
}

Now a simple cross of a,b,c,d would create 256256257*256 = 232 cross bins. Bins of a cross are automatically generated and you only specify bins if you want them merged or ignored. If are only interested in the cases where (a==b) && (c==d), you have ignore all the other bins with

abcd: cross a,b,c,d {
   ignore_bins not_equal = abcd with( a!=b || c!=d);
}