Systemverilog: cross Coverage and Ignore bins

SystemVerilog
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2

In reply to Chakrakirthi:

You had a couple of issues with the posted code. The bins cannot all be named
c1, and the 4th bin should have the range
[2:120]. Then the bins you should ignore are

covergroup cg_XY;
   cp_x: coverpoint X {bins x_b[] = {[1:20]};}
   cp_y: coverpoint Y {bins y_b[] = {[1:14]};}
   cp_XY: cross cp_x, cp_y {
      bins c1 = binsof(cp_x.x_b) intersect {1} && binsof(cp_y.y_b) intersect {1};
      bins c2 = binsof(cp_x.x_b) intersect {1} && binsof(cp_y.y_b) intersect {[2:14]};
      bins c3 = binsof(cp_x.x_b) intersect {2} && binsof(cp_y.y_b) intersect {[3:14]};
      bins c4 = binsof(cp_x.x_b) intersect {[2:20]} && binsof(cp_y.y_b) intersect {1};
      ignore_bins c5 = binsof(cp_x.x_b) intersect {2} && binsof(cp_y.y_b) intersect {2};
      ignore_bins c6 = binsof(cp_x.x_b) intersect {[3:20]} && binsof(cp_y.y_b) intersect {[2:14]};
   }
endgroup

Using the
with construct might be easer to read and closer to what your requirements look like.

covergroup cg_XY;
   cp_x: coverpoint X {bins x_b[] = {[1:20]};}
   cp_y: coverpoint Y {bins y_b[] = {[1:14]};}
   cp_XY: cross cp_x, cp_y {
      bins c1 = cp_XY with (cp_x==1 && cp_y> 1);
      bins c2 = cp_XY with (cp_x==2 && cp_y> 2);
      bins c3 = cp_XY with (cp_x==1 && cp_y==1);
      bins c4 = cp_XY with (cp_x >1 && cp_y==1);
      ignore_bins c5 = cp_XY with (cp_x==2 && cp_y==2);
      ignore_bins c6 = cp_XY with (cp_x >2 && cp_y >1);
   }
endgroup