SystemVerilog Constraint to populate unique values into a 2d fixed-size array without using the unique keyword

SystemVerilog
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4

In reply to sfenil1804:

Could you please explain whats happening in the two foreach loops ? why do we need the condition !(a==i && b==j) ? is the first foreach loop creating a randomized matrix and the second matrix trying to make the elements unique by iterating the first one ?

constraint unique_elements {foreach (array[i][j]) {
    foreach (array[a][b]){
      (!(a==i && b==j)) -> array[a][b] != array [i][j];
    }
  }}