Systemverilog constraint to find a max Square root of a certain number？

SystemVerilog
1 

program main ;
   typedef int unsigned uint;
   initial begin
      uint valid_size;
      assert(std::randomize(valid_size) with {
         (valid_size)**2 <= 99967;
         (valid_size+1)**2 > 99967;
      });
      $display("valid_size = %d, %0d", valid_size, $sqrt(99967));
   end
endprogram

above code give me the result：

valid_size = 1895153639, 316

why this situation happens?

2

In reply to zhajio1988:

Please read A Little Verilog Knowledge Goes A Long Way in Understanding How SystemVerilog Constraints Work - Verification Horizons