SystemVerilog Constraint an Assume Statement for Formal Verification

SystemVerilog
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1

I am writing Assertion for Formal Verification and Wanted to constraint an Input using Assume.
How do i constraint a signal A[3:0] to only have values between 1 to 8 for my State Space

property p_A;
@(posedge clk)
// Range for A to be between 1 to 8
endproperty : p_A

ap_A: assume property (p_A);
2

In reply to priyansh.ag:

 
module m;
  bit clk;
  bit[3:0]a;
  
  property p_A;
    @(posedge clk)
// Range for A to be between 1 to 8
       a inside{1,8};
  endproperty : p_A

  ap_A: assume property (p_A);
endmodule