SystemVerilog Checker

SystemVerilog
,
7

In reply to Rohi_417:
Multiple smaller assertions is a preferred approach here.


// Requirements: 
// 1.After REQ assert, ACK has to be asserted in 1~10 clk cycle
ap_req2ack: assert property(  
    @(posedge clk) $rose(req) |-> ##[1:10] $rose(ack) );  
// 2.REQ should stay high for 5~7 clk cycles before goes low
ap_reqHi: assert property(  
    @(posedge clk) $rose(req) |-> req[*5:7]);
//3.After ACK assert, REQ has to be de-asserted in 1~10 clk cycle 
ap_ack2req: assert property(
     @(posedge clk) $rose(req) |-> $rose(ack) [->1]  
                                   ##[1:10] $fell(req) );

There are some bugs in the task solution (it was not tested).
Will post an update, as the task approach showed errors when compared to the SVA solution.
And that proves that SVA is preferred, with few exceptions as explained in my paper.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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