In reply to mlsxdx:
Hi, can someone help on implementing checking the timing without using SVA?
The timing definition of two signals-(REQ, ACK) are as follows:
1.After REQ assert, ACK has to be asserted in 1~10 clk cycle
2.REQ should stay high for 5~7 clk cycles before goes low
3.After ACK assert, REQ has to be de-asserted in 1~10 clk cycle
Hi,can you please write assertion for this ?