For all i know till now about assertion based verifation ,
Syntax are like
assert property (@posedge clk) ($rose(start) ##1 transfer)
means that transfer should come after one clock cycle if posedge of start comes at clk.
Now in my case there is no clock .
So i want to specify timings say 5ns .
How do i do that ?
In reply to aman.21:
I guess SystemVerilog simulator do needs a triggering point. If no clock is provided then It may take simulation clock as a reference. The assertion with no clock will be triggered at each simulation clock.
In order to answer above question you can move second half into sequence and call a sequence from property.
assert property (@posedge clk) ($rose(start) ##1 transfer)
means that transfer should come after one clock cycle if posedge of start comes at clk.
Now in my case there is no clock. So i want to specify timings say 5ns .
How do i do that ?
Every assertion needs a leading clocking event. in your example above, the leading clocking event is @(posedge clk). BTW, this is a poorly written assertion; you need an implication operator.
ap_start_xfr: assert property (@posedge clk) ($rose(start) |=> transfer);
If what you want to do is that start is clocked by @(posedge clk), and 5ns later you want to check that transfer is a 1’b1. Below is an example on how you can do that (basically create an event that occurs 5ns after the @(posedge clk). I did it after the occurrence of “a”.
module lce1;
bit a, b, clk;
event e;
initial forever #50 clk=!clk;
always @(posedge clk) begin
if (!randomize(a, b)) $error();
if(a) begin
#5;
-> e;
end
end
assert property(@(posedge clk) $rose(a) |-> @e b );
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
