SystemVerilog Assertions: There should be maximum two requests in 10 clock cycles

SystemVerilog
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2

In reply to Ramakrishna Melgiri:

A quick, untested variant - for you to try:


property should_be_max_two_requests_in_ten_cycles(cb,sig0,sig1,sig2);
@(cb)	(sig0 |=> (sig1[->2] ##1 sig2) within 1'b1[*10];
endproperty:	should_be_max_two_requests_in_ten_cycles

You will need to fix the braces and perhaps the within operator’s applicability etc.

Am glad you are using a simple, unit test to verify this assertion. We will be demonstrating a similar concept with SVA examples and the unit tests shall be in Go2UVM framework. We will also use SVUnit’s UVM Report mock to expect/unexpect error. Stay tuned to DVCon India for the slides/paper.

Srini
www.go2uvm.org