Systemverilog assertion

SystemVerilog
,
8

In reply to wangjiawen:


ap_abc2_want: assert property(@(posedge clk) 
                   first_match(a ##1 (!b[*0:$] ##1 b ##1 !b[*1:$] and 
                                      !c[*0:$] ##1 c ##1 !c[*1:$] )) |-> $past(d));
// is same as 
ap_abc2_want2: assert property(@(posedge clk) 
                   first_match(a ##1 (b[->1] ##1 !b[*1:$] and 
                                      c[->1] ##1 !c[*1:$])) |-> $past(d));
// Looks cleaner