In reply to ben@SystemVerilog.us:
Hi Ben,
Thanks a lot for the reply! I did not know the difference between “and” and “&&”. Really appreciate your help.
Regarding your second comment, I indeed used implication operator, but the position is different.
Mine: a ##1 (b[->1] and c[->1]) |-> ##1 d;
Yours: a |-> (b[->1] and c[->1]) ##1 d;
I guess the difference between yours and mine is that in my code the assertion won’t be checked until the whole sequence before the a implication operation is satisfied, but in your code, every time a is asserted, the assertion will start. In my opinion, there is some difference here, but for the current requirement, both should work. Not sure if I get your point correctly? Please correct me if I’m wrong.
Thanks again for your help!