SystemVerilog Assertion label

In reply to markylew:
You have to look at the syntax.
1800’2018 16.3 Immediate assertions


immediate_assertion_statement ::=
   simple_immediate_assertion_statement
 | deferred_immediate_assertion_statement
...
simple_immediate_assert_statement ::=
  assert ( expression ) action_block

action_block ::=
statement_or_null
| [ statement ] else statement_or_null

 ERR_reset_went_unknown: assert(!$isunknown(Reset))  // assert ( expression )
    else  $error("ERR_reset_went_unknown");  // [ statement ] else statement_or_null
// note that from the syntax on the action_block the [statement] is optional. 
// thus, thus the following is in ERROR
assert(!$isunknown(Reset)); else  $error("ERR_reset_went_unknown"); 
// because 
assert(!$isunknown(Reset));  // this follows the syntax of 
assert ( expression ) null; // The ";" is the end of simple_immediate_assert_statement 
// so what you have 
assert(!$isunknown(Reset));  // a legal statement, DONE here with that statement 
else  $error("ERR_reset_went_unknown"); // else?  no legal statement starts with "else' 
// what is that funny "else' statement? It's hanging there!! illegal!

Ben SystemVerilog.us