Systemverilog assertion - How do I check the stable signal after implication operator?

SystemVerilog
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3

In reply to UVM_LOVE:


the following assertion will check idle is high as long as reset is low.  what will be the value of idle when reset transition to high. 
property reset_chk0_p;                                         
  @(posedge clk)                                               
    $fell(reset) |-> ##[0:1] idle ##0 idle[*0:$] intersect !reset[*0:$] ##1 $rose(reset);
endproperty