Systemverilog assertion - How do I check the stable signal after implication operator?

SystemVerilog
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2

In reply to UVM_LOVE:


$fell(reset) |-> ##[0:1] idle[*1:$] intersect $rose(reset)[->1];

Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.

or Cohen_Links_to_papers_books - Google Docs

Getting started with verification with SystemVerilog